The ARM virtual memory model provides features for operating system developers to mitigate unnecesary TLB flushes. For example, ARM TLB’s can match entries based on the current exception level, remov- ing the need to flush the TLB when taking an exception.
Similarly on x86, a vm exit into root mode will not cause a TLB flush. In addition, ARM defines a unique application specific identifier (ASID) that an OS assigns to each user process. ASID’s are commu- nicated to the hardware through the top sixteen bits of TTBR0_EL1. During an address translation, the hard- ware matches TLB entries using the ASID, removing the need to flush the TLB during a context switch. On x86, a similar mechansim is provided called the process-context identifier (PCID).