sargx digital garden

Secondary Level Address Translation (SLAT)

1 min read

![[Untitled 137.png|https://trustworthy.systems/publications/theses_public/10/Varanasi%3Abe.pdf]]

![[Untitled 138.png|https://trustworthy.systems/publications/theses_public/10/Varanasi%3Abe.pdf]]

  • Intel x64 : EXTENDED PAGE TABLES (EPT)
  • ARM: STAGE 2 TRANSLATION (S2T)

INTEL x64:

If running in VMX non-root mode (i.e. in a VM) and EPT is enabled then:

Logical address   -->   GDT -->  Linear address          --> Page tables --> Guest Physical Address --> EPT --> (System) Physical Address
(segment:offset)                 (segment base + offset)         
 
\______________________________________________________/                      \__________________________________________________________/
                  Virtual address                                                        Physical address
             (can be either logical or linear)

Virtualization of the IOMMU is performed by a complementary technology to EPT called VT-d.

https://revers.engineering/mmu-ept-technical-details/

🌱 Back to Garden

Graph View

Backlinks