FPGA

RoadMap

RISC-V

VERILOG

MCU + FPGA

Content

Testbenchs

High Level Synthesis (HLS)

Formal Verification

SystemVerilog (evolution of Verilog)

Implementations

PROVIDERS

https://aws.amazon.com/pt/blogs/aws/developer-preview-ec2-instances-f1-with-programmable-hardware/

TOOLS

Innovate by reaching for the open source FPGA tooling:

https://f4pga.org/

Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures.

https://github.com/sylefeb/Silice

https://olofkindgren.blogspot.com/2022/10/from-simulation-to-soc-with-fusesoc-and.html

3D raytraced game with open source C to FPGA toolchain

https://blog.yosyshq.com/p/3d-raytracing/

SIMULADORES ONLINE

http://digitaljs.tilk.eu/

https://www.veripool.org/verilator/

SIMULATORS

https://www.zeroasic.com/blog/switchboard-release

https://github.com/zeroasiccorp/switchboard/

CONTENT REPOS

https://www.fpga4fun.com/

https://github.com/FPGA-Systems/fpga-awesome-list

TESTBENCH

https://www.fpgatutorial.com/how-to-write-a-basic-verilog-testbench/

BOOKS

https://link.springer.com/book/10.1007/978-3-319-42438-5

https://www.dspguide.com/

https://link.springer.com/book/10.1007/978-3-642-45309-0

https://kastner.ucsd.edu/hlsbook/

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